This invention relates to a field effect transistor semiconductor device and is particularly, though not exclusively, concerned with the trade off relationship between the on-resistance and the breakdown voltage of the device.
It is well known that the voltage blocking capability of a field effect transistor device can be increased by reducing the dopant concentration and increasing the size of the drain drift region. However, this also increases the resistivity and length of the majority charge carrier path through the device when the device is conducting. This means that the series resistivity of the current path for majority charge carriers through the device, and thus the on-resistance of the field effect device, increases in proportion to approximately the square of the desired breakdown voltage.
U.S. Pat. No. 4,754,310, the contents of which are hereby incorporated herein by reference, (our reference PHB32740) addresses this problem by providing the drain drift region as a zone formed of first regions of one conductivity type interposed with second regions of the opposite conductivity type with the dopant concentrations and dimensions of the first and second regions being such that, when the device is operated in voltage blocking mode and the zone is depleted of free charge carriers, the space charge per unit area in the first and second regions balances at least to the extent that the electric field resulting from the space charge is less than the critical field strength at which avalanche breakdown would occur. This enables the required breakdown voltage characteristics to be obtained using interposed semiconductor regions which individually have a higher dopant concentration, and thus lower resistivity, than would otherwise be required so that the series resistivity of the first and second regions and thus the on-resistance of the device can be lower than for conventional devices.
For best results using the invention of U.S. Pat. No. 4,654,310 the charge balance between each pole in the drain drift region needs to be precise. That is to say the integral of the doping concentration perpendicular to the junction of the two interposed regions of one conductivity type and opposite conductivity type needs to have the same value of about 2xc3x971012 cmxe2x88x922. Doping concentration to this level of precision in integrated circuit processing techniques is difficult, and a small fluctuation in doping concentration in either of the two regions results in a correspondingly large deviation from the desired charge balance along the drain drift region and a corresponding large reduction in the breakdown voltage of the device.
International patent application published as W001/59847, the contents of which are hereby incorporated herein by reference, (our reference PHNL 000066) provides another way of improving the trade off between breakdown voltage and on resistance in the case of vertical high voltage insulated gate field effect devices. Field shaping regions extend through the drain drift region from the body regions of the device to the drain region. These field shaping regions are semi-insulative or resistive regions which provide current leakage paths from the source regions when the device is non-conducting and a voltage is applied between the main electrodes of the device so as to cause an extension of a depletion region in the drain drift region towards the drain region to increase the breakdown voltage of the device. The small leakage current along the resistive paths causes a linear electrical potential drop along these paths. Hence a substantially constant vertical electric field is generated along these paths and accordingly in the adjacent drain drift region, and this results in the breakdown voltage being greater than for a non-uniform electric field which would occur in the absence of the field shaping region. Thus, as for the invention of U.S. Pat. No. 4,754,310, for a given required breakdown voltage of the device, it is possible to increase the doping concentration of the drain drift region and hence reduce the on-resistance of the device compared with a conventional device.
An object of the present invention is to provide a field effect transistor semiconductor device which also has a field shaping region adjacent the drift region but in which the substantially constant electric field is generated in the field shaping region in a different manner and by a different structure.
According to the present invention there is provided a field effect transistor semiconductor device comprising a source region, a drain region and a drain drift region, the device having a field shaping region adjacent the drift region and arranged such that, in use, when a voltage is applied between the source and drain regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region and accordingly in the adjacent drift region, characterised in that the field shaping region is arranged to function as a capacitor dielectric region between a first capacitor electrode region and a second capacitor electrode region, the first and second capacitor electrode regions being adjacent respective ends of the dielectric region and having different electron energy barriers.
By substantially constant electric field it is meant herein that the maximum electric field in the field shaping region and hence in the adjacent drift region at a given voltage is reduced in comparison with the absence of the field shaping region with the consequence that the breakdown voltage of the device is comparatively greater. Associated with the reduced maximum electric field is an increased integral of the electric field along the length of the field shaping region and the drift region and hence the greater breakdown voltage. It is possible to have a perfectly uniform electric field along both the field shaping region and the adjacent drift region but that depends on a number of factors including the device geometry, for example the extent of the field shaping region along the length of the drift region and the extent of influence of the field shaping region across the width of the drift region.
In a device according to the present invention, it is the different electron energy barriers of the first and second capacitor electrode regions which ensure that in use, when a voltage is applied between the source and drain regions and the device is non-conducting, the field shaping region functions as a capacitor dielectric region rather than a resistive region, there is substantially no space charge in the field shaping region, and within the drift region there is a charge balance between the space charge in the first capacitor electrode region, together with the drain drift region, and the second capacitor electrode region. That is to say, the charge in the drain drift region plus the charge in the first capacitor electrode region compensates the charge of, the second capacitor electrode region. It is an applied voltage which capacitively generates the substantially constant electric field in the field shaping region in the present invention rather than the leakage current applied through the field shaping region which is provided in the arrangement disclosed in W001/59847. Also, the problem with the arrangement of U.S. Pat. No. 4,754,310 of providing a precise charge balance between the two opposite conductivity type regions along the length of the drift region does not arise in the arrangement of the present invention.
In a device according to the present invention, the capacitor dielectric region may be intrinsic semiconductor material, or it may be extrinsic semiconductor material which is lower doped than the drift region, or it may be semi-insulating material, for example comprising one of oxygen doped polycrystalline silicon and nitrogen doped polycrystalline silicon.
In a device according to the invention, the capacitor dielectric region may be separated from the drain drift region by an insulating region. This insulating region tends to inhibit the possibility of conduction between the capacitor dielectric region and the drain drift region, and it is also advantageous for the device performance regarding interface states. It may be possible that because of the non-ideal interfaces parasitic charge is induced. These interface states are reduced by an insulating layer. However, the electric field produced in the drift region will still be sufficiently uniform for the purpose of this invention in the absence of this insulating region.
In a device according to the invention, the first capacitor electrode region may be a semiconductor region of one conductivity type with the second capacitor electrode region being a semiconductor region of opposite conductivity type to the first capacitor electrode region. In this case the different electron energy barriers of the first and second capacitor electrode regions are provided by the different work functions of the two semiconductor conductivity types. Alternatively, the first capacitor electrode region may be a semiconductor region with the second capacitor electrode region being a Schottky barrier region. In this case the work function of the first capacitor electrode semiconductor region is an electron energy barrier which is different from the Schottky electron energy barrier of the second capacitor electrode Schottky barrier region. In both cases as just specified, the first capacitor electrode region semiconductor region is of the same conductivity type as the drain region.
In a device according to the invention, the transistor may be an insulated gate field effect transistor. This may be a vertical transistor which may be a trench-gate transistor.
The invention of W001/59847 discussed above is disclosed in relation to vertical high voltage insulated gate field effect devices. The vertical trench-gate transistor devices as defined just above in accordance with the invention may also be high voltage devices, that is with breakdown voltages above about 200 volts, where the on resistance of the device is mainly determined by the resistance of the drain drift region. However, for reasons explained later, these vertical trench-gate devices in accordance with the invention may also be medium or low voltage devices, that is with breakdown voltages respectively below about 200 volts or below about 50 volts. For 50 volts and less the on resistance of the device is mainly determined by the resistance of the channel accommodating region. For these medium and low voltage devices it is advantageous, for reasons also explained later, to have the gate insulation at the bottom of the trench-gate greater than the gate insulation adjacent the channel accommodating region so as to reduce the gate to drain charge of the transistor. In this case, the gate insulation at the bottom of the trench-gate may be of the same material as the gate insulation adjacent the channel accommodating region but of greater thickness.
In a device according to the invention where the transistor is an insulated gate field effect transistor, this may be a lateral transistor having the source region, the drain region and the drift region underneath a top major surface of the device, wherein a planar insulated gate is above said top major surface, and wherein the capacitor dielectric region and the first and second capacitor electrode regions are above said top major surface. Alternatively, the insulated gate field effect transistor may be a lateral transistor having the source region, the drain region and the drain drift region underneath a top major surface of the device, wherein the drain drift region is divided into laterally spaced sections, and wherein the capacitor dielectric region is underneath the top major surface and is divided into laterally spaced sections which alternate with the drain drift sections. In this case, the insulated gate may extend below the top major surface at the end of the drain drift sections opposite the drain region, or a planar insulated gate may be above the top major surface.
In an insulated gate field effect transistor device according to the invention, the transistor may be an insulated gate bipolar transistor having a semiconductor region of opposite conductivity type to the drain region between the drain region and a drain electrode.
The field effect transistor devices according to this invention may be used in direct current power applications. They may also be used in radio frequency applications. The effect of the field shaping region is not only to enable the on resistance of the device to be decreased for a given breakdown voltage which is important for DC power applications, but also to increase the cut off frequency for a given breakdown voltage which is important for RF applications. Also, the fact that the field shaping region functions as a capacitor dielectric region rather than a resistive region (as is the case for example in W001/59847), and that there is substantially no space charge in the field shaping region when a voltage is applied between the source and drain regions, improves the switching speed of the device which is important for RF applications. In the case specified above where the second capacitor electrode region is a semiconductor region, then the switching speed may be improved by choice of the type of semiconductor for this second capacitor electrode region, for example by choosing silicon-germanium rather than silicon. Furthermore, the switching speed is improved in the case specified above where the second capacitor electrode region is a Schottky barrier region rather than a semiconductor region. Where the devices are insulated gate field effect transistor devices as specified above, then the above-specified lateral transistor devices are particularly suitable for RF applications.
In a device according to the invention, instead of the transistor being an insulated gate field effect transistor it may be a Schottky gate field effect transistor. Schottky gate field effect transistors are known to be suitable for RF applications. The Schottky gate field effect transistor in a device according to the invention may be a vertical transistor. Alternatively this transistor may be a lateral transistor having the source region, the drain region and the drain drift region underneath a top major surface of the device, wherein the Schottky-gate is above said top major surface, and wherein the capacitor dielectric region and the first and second capacitor electrode regions are above said top major surface.
In a device according to the invention there are different possibilities for connection of the first and second capacitor electrode regions to device electrodes. In one case, the first and second capacitor electrode regions may be respectively connected to drain and source electrodes. In another case, the first and second capacitor electrode regions may be respectively connected to drain and gate electrodes. In yet another case, at least one of the first and second capacitor electrode regions may be connected to an electrode which is not a drain, source or gate electrode. A possible advantageous use for this last case is where the device is an RF power device so that only a constant DC voltage, or current, may be applied to the field shaping region via the first and second capacitor electrode regions while the drain source and gate electrodes are used for application of the RF signal together with this constant DC voltage, or current.
In a device according to the invention, except for the last case for connection of the first and second capacitor electrode regions mentioned just above, the first capacitor electrode region may be integral with the drain region.